ARM Cortex-M0 SoC Design
3 days

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Overview

ARM® Cortex™-M0 SoC Design is a 3-day class for engineers designing SoC based around the ARM Cortex-M0 core. The ARM Cortex-M0 is the smallest ARM core especially designed and optimised for low power. The core has many things in common with the ARM Cortex-M architecture family. This class concentrates on the specific information needed to integrate this core into the System on Chip environment. The class includes not only an introduction into the ARM architecture, Cortex-M0 programmer's model, AMBA on-chip bus architecture and Cortex-M0 debug architecture options, it looks in detail at the Cortex-M0 Power Management architecture and the Interrupt behavioural of this core.

The class includes a number of worked examples developed by ARM to reinforce the lecture material.

Who should attend?

Hardware and system design engineers who need to understand the issues involved when designing SoC's around the ARM Cortex-M0 core. Engineers who need to develop and write software for the ARM Cortex-M0 can attend our ARM Cortex-M(3) software class. The differences between M0 and M3 are minor from the software point-of-view and will be explained in that class.

Pre-requisites

Some knowledge of embedded systems and familiarity with digital logic and hardware/ASIC design issues. A basic awareness of ARM is useful but not essential.

Training materials

This class uses training materials developed by ARM®.

Structure and content

• Introduction to the ARM Architecture
• Cortex-M0 Overview
• Cortex-M0 Programmer's Model and Instruction Set
• Cortex-M0 Processor Core
• Interrupt and Exception Handling
• Cortex-M0 Memory Map and Memory Types
• Cortex-M SysTick timer
• Cortex-M0 System Interfaces
• Cortex-M0 Clocks, Power Management
• Cortex-M0 Debug Architecture options
• Cortex-M0 Integration & Implementation

Hands-on exercises can be done using MDK (Keil IDE) or Eclipse / RVDS

ARM and Cortex-M0 are registered trade marks of ARM Holdings Plc.

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