Expert SystemC
Verification
2 days

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Overview

Expert SystemC Verification is a 2-day advanced training course teaching existing SystemC users how to use SystemC for testbench automation using a constrained random verification methodology. This class, supporting versions 1.0p2 of the SystemC verification library (SCV), teaches delegates how to debug and validate models, and exploit the library.

Course workshops are based around carefully designed exercises to reinforce and challenge the extend of learning, and comprise approximately 50% of class time.

Doulos has a world-wide lead in independent SystemC know-how having been active in SystemC-based methods since 2000. We have delivered SystemC training and support to engineers in more than 100 companies world-wide – including direct involvement with methodology and tool developers in such companies as ARM, Cadence, CoWare Mentor Graphics and Synopsys.

Who should attend?

• Verification engineers with a sound knowledge of SystemC and C++, who wish to use constrained random verification using SCV
• Hardware and software engineers who are currently using SystemC, and wish to learn the constrained random verification methodology with SCV.
• Users of Cadence Testbuilder who wish to have an introduction to SCV/CVE.

What will you learn?

• The constrained random approach to verification
• The SCV core classes and facilities
• How to use SCV to debug and validate your models
• How to best exploit SCV and transaction level modelling
• (Optional) The additional features in Cadence Verification Extensions (CVE 5.3s001)

Pre-requisites

Delegates must have a good working knowledge of SystemC, such as may be gained from attending the Doulos course Comprehensive SystemC. No previous knowledge of constrained random verification is needed, as this will be introduced during the course.
Please contact AmbLot direct to discuss and assess your specific experience against the pre-requisites

Training materials

Doulos Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Fees include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples and solutions to help you apply your knowledge
• Doulos SystemC Golden Reference Guide for language, syntax, semantics and tips.

Structure and Content

Verification Methodology

Black and White Box Testing • Simulation and coverage • Verification Methodology Overview • What is Testbench Automation? • How SystemC and SCV fit in to verification • Obtaining SCV

Data Introspection

Extensions to data • Static vs Dynamic extensions • Extensions components • Extending built-in data types • Extending User Defined Data Types • User-defined data types with private attributes • Accessing Static Data Extensions

Randomization

Randomization • Dynamic extensions • Shared (reference-counted) pointers • Smart Pointers • Randomizing user defined data • Weighted distributions using bags • Weighted distributions using keep • Reproducibility • Using Seed Files

Constraints

Why we need constraints • Hard vs Soft • Creating constraints – scv_constraint_base • Constraining a simple data type • Constraining a user data type • Enabling and disabling constraints • Methods vs attributes • Overloading next() • Hierarchical Constraints

Transaction Recording

Requirements for transaction recording • Stream, generators, databases • Creating output • Transaction attributes • Using the transaction database

Other SCV Features

Using SCV_REPORT • The HDL Connection API • SCV data types (scv_sparse_array)

SystemC 2.1 Dynamic Threads

Dynamic Thread Applications • Spawning Threads and Methods • Setting spawn options • Spawning functions • Spawning member functions • scx_barrier

Cadence Verification Extensions (CVE) [optional]

CVE Wizards • Connecting to ncsim • Recording to an SDI database • Dynamic Thread Creation • Other data types (smart queues)

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