Expert Verilog
5 days

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Overview

Expert Verilog® is an intensive 5-day advanced application course. It teaches engineers how to increase productivity by enhancing their Verilog coding and application skills. Presented in two distinct modules, Expert Verilog focuses on language and synthesis issues, design re-use, test banches and the latest verification techniques - including PSL and an introduction to modern assertion-based approaches to verification. Each module now also includes an overview of the new SystemVerilog extensions to Verilog, with an assessment of their impact on both Design and Verification.

• Expert Verilog® Design (2 days) for design engineers wishing to deepen their knowledge of both RTL and synthesis using Verilog, and to improve their Verilog coding style with design re-use in mind. Design for Verification is also covered with an introduction to PSL and modern assertion-based techniques.
• Expert Verilog® Verification (3 days) for design engineers and verification engineers involved in Verilog test bench development, or behavioural modelling, for the purpose of functional verification.

The modules, which may be attended together or independently, follow on from the industry standard Doulos course, “Comprehensive Verilog®”. Carefully designed workshops comprise 50% of teaching time, and enable engineers to apply their new skills in the context of the latest Verilog design tools, practices and methodologies.

What will you learn ?

• A deeper understanding of the Verilog language and how to apply it, enabling you to troubleshoot Verilog simulation and synthesis problems more easily.
• How to produce smaller and faster hardware designs using Verilog with RTL synthesis tools.
• A Verilog coding style to facilitate code re-use and best practice in how to package IP.
• How the new revision of the Verilog language (IEEE 1364-2001) and the SystemVerilog extensions will impact and enhance your design and verification activity.
• How best to tackle the problem of design verification using Verilog - the principles and practice.
• Advaced testbenching - how to structure and write large and complex Verilog test benches.
• Techniques for writing behavioural models of hardware components in Verilog.
• How to incorporate PLI applications into youe Verilog simulations.

Prerequisites

This is an advanced language and methodology training course. Prior attendance of the Doulos "Comprehensive Verilog®" ( or equivalent) is required, and at least 6 months of "live" project experience using Verilog is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis, using Verilog.

Course materials

Doulos course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them soughht after resources in their own right. Course materials include :

• Fully indexed course note creating a complete reference manual
• Workbook full of practical examples to help you apply your knowledge
• Doulos Verilog Golden Reference Guide for language syntax, semantics and tips
• Complimentary PSL Golden Reference Guide, which includes coverage of OVL
• Tool & Technology tour booklet (to support the tools and technologies of your choice)

Structure and content

Expert Verilog® Design (days 1-2)

RTL

Appreciating the finer points of syntax directed translation Incomplete assignment, latches and re-circulation •Using blocking and non-blocking assignments •Asynchronous inputs to clocked processes •Inference versus instantiation •The limits of combinational, register and arithmetic optimisation •Using hierarchy to control synthesis •Timing constraints, area constraints, and optimisation options •Multiple clock edges and partitioning clock domains •Synthesis methodology for large designs •Coding styles for efficient and maintainable designs •Implementing sequential algorithms in RTL •Bit-serial processing, pipelining and speed/space tradeoffs

Behavioural Synthesis

Design flow and tool flow •The architecture generated by BS •Scheduling, allocation, and the trade-offs •Chaining and multi-cycle operations •I/O modes •Approach to verification •Handshaking •Scheduling constraints •Local versus process-wide variables, I/O registers and register sharing •Placement of wait statements •How to structure a process •Resets •Loops •Pipelining •Memory inference

IP and Reuse with Verilog

Language level re-use •Standard component re-use •General re-use •Economic payback from re-use •Re-use culture •Packaging IP for re-use •Documenting IP, including test cases •Impact of IP on design flow planning •Impact of IP on revision control, bug tracking, archiving •Writing re-usable Verilog •RTL Verilog style for capturing IP •Hierarchy and partitioning •Isolating tool and technolgoy dependencies •Readability and maintainability •Comments and meaningful names •Identifying generalisable properties •Language facilities for re-use, including Verilog-2000 improvements

Design for Verification with assertions

Why use assertions in your designs •Introduction to properties •Property languages •Property specification Language (PSL) •Introduction to temporal operators

Verilog-2001 in your Designs

A tutorial review of the major new features of Verilog-2001 that are relevant to design

SystemVerilog - An overview

A tutorial review of the SystemVerilog and its impact

Expert Verilog® Verification (jours 3-5)

Verification Strategies

Verification flow •Black and white box testing styles •Code analysis to guide testing •Techniques for stimulus generation and output checking

Advanced Verilog for Verification

Fine-grain concurrency with fork/join •The Verilog simulation cycle and its impact on coding style •Non-determinism and race hazards •Understanding the effect of delayed signal assignments

Improving the Quality of your Test Fixture Code

Structuring test fixtures with tasks and functions •Tactics for packaging code for maintainability and re-use •Advanced stimulus generators: serial data, complex timing> •Software encapsulation: modules, local variables, multiple hierarchies

Transaction-Based Test Fixtures

Bus functional models •Techniques for layering your test fixtures •Using Verilog modules like OO classes •Transaction generation using bus functional models •Re-use and flexibility of test fixture code

Monitoring

Specify blocks •Built-in timing checks •Strobing inputs and sampling outputs •Measuring delays •Storing inputs/outputs in a buffer •Collecting and filtering diagnostic data •Simple data visualisation techniques

Component Modelling Introduction

Uses of component modelling •Component modelling methods •Choosing a component model •Structure of a component model •Handling asynchronous inputs •Storing inputs/outputs and sampling outputs •Measuring delays

Modelling and Analysis Techniques

Modelling memories •Imitating dynamic allocation in Verilog •Using public domain PLI applications to model large memories •Modelling external analogue subsystems •Signature analysis and other techniques for regression testing •Varying the timing of stimulus •Modelling communcations channels •Random and directed-random tests

Using PLI Libraries

(note: no prior experience of C is assumed)
Incorporating PLI applications into your simulations •What the PLI can and can't do •Two generations of the PLI - which to use? •Types of PLI application: functions, stimulus generators, file access, component models •Pointers to functions in C •Function pointer tables •PLI application integration in various simulators

Co-simulation Tools or Writing PLI Applications (optional modules)

The PLI option requires a working knowledge of the C programming language.

Co-simulation Tools

Simulating mixed-language systems •Simulating software execution in an embedded system •Types of co-simulation environment •Conflicts between software and hardware simulation - memory models, synchronisation •Data representations - fixed point, floating-point •The future - C and C++ as hardware description languages

Writing PLI Applications

PLI jargon •VPI and TF/ACC routines •Creating a simple PLI application •Linking PLI code to your Verilog simulation •Callback functions w Stimulus generators •Making PLI applications sensitive to input changes •Writing component models in the PLI

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